1. Field of the Invention
The present invention relates to a wafer level packaging, and more specifically to form spacer walls and sealant on a wafer or transparent substrate at a wafer level package.
2. Description of the Prior Art
In recent years, since the circuit devices in a chip are manufactured with a high density, the IC package is also developed to high density, high efficiency and miniaturization. Typically, the packaging can protect the dies from moisture and mechanical damage. In the technology, the semiconductor dies or chips are usually individually packaged in a plastic or ceramic package after accomplishing wafer fabrication. The function of the packaging includes power distribution, signal distribution, heat dissipation, protection and support. As a result, the packaging technique is influenced by the development of integrated circuits, and the trend in electrical products is to have high integration with a small size. Therefore, the integrated circuits will be minimized so that the logic circuits within a chip or die are greatly enhanced, and the input/output (I/O) pins are also increased. In order to coordinate with the requirements and alterations as above, various types of packaging have recently been developed, for instance ball grid array (BGA), chip scale package (CSP), multi chip module package (MCM package), tape carrier package (TCP) and wafer level package (WLP) etc.
No matter what type of packaging, most of the packaging is divided into individual chips before they are packaged. However, the packaging at the wafer level is a trend in semiconductor packaging. Typically, the wafer level package utilizes the whole wafer as an object, not utilizing a single chip or die. Hence, before performing a scribing process, packaging and testing must be accomplished. This is an advanced technique so that the process of wire bonding, mold, die mount and assembly can be omitted so do lead frame and substrate. Therefore, the cost and manufacturing time will be reduced. On the other hand, the process in traditional packaging includes, die saw, die mount, wire bond, mold, trim, mark, plating and inspection etc.
A conventional packaging will be described with reference to FIG. 1A to 1C. Referring to FIG. 1A, providing a semiconductor wafer 101 and a transparent substrate 113 firstly, the semiconductor wafer 101 comprises pluralities of dies 103 thereon, further, the pluralities of dies 103 utilize the semiconductor processes so as to manufacture pluralities of microcircuits thereof (not illustrated). Next, referring to FIG. 1B, each of the dies 103 on the semiconductor wafer 101 is individually separated by a dicing saw machine so that a plurality of individual dies 103 is obtained. Then, the individual dies 103 are placed on a semiconductor wafer 105 by a pick and place arm of a die bonder and then adhered by an epoxy (not illustrated). The semiconductor substrate 105 comprises borders 107, wherein the borders 107 are obtained from a mold with a particular pattern and the semiconductor process. As a result, each individual chip 103 is placed on the semiconductor substrate 105 by a die bonder in the process of a die mount. Thus, the individual dies 103 are easily dropped, resulting in the gross amount of semiconductor wafer 101 dies are greatly reduced, moreover; the yield will be decreased. Thereafter, performing a process of wire bonding in order to transfer the signal from the individual dies 103 to the outside. The process of wire bonding comprises, gold bonding wire 109 wire bonds on the individual dies 103.
Subsequently, as shown in FIG. 1C, after adhering and placing each individual dies 103 on the semiconductor substrate 105, performing a process of mold, wherein a sealant 111 is coated on the borders 107 and then a transparent substrate 113 is covered thereon.
Another process of the sealant is refereed to TFT-LCD process, wherein the spacer balls (not illustrated) are randomly mixed with the sealant 111. The function of the sealant 111 is that the upper substrate of the liquid crystal pannel can adhere compactly with lower one, more, isolating the liquid crystal from the outside. The spacer balls are provided as a support between the upper substrate and the lower substrate. However, the spacer balls have become spheroids while the transparent substrate 113 is a cover. Also, the spacer walls shape is not regular so that the width of the sealant 111 is hard to control, further; the uniformity of the gap, which is between the upper substrate and the lower substrate, is not able to be maintained. Hence, the electric field is variously distributed so that the gray level of the liquid crystal is influenced. Due to the fact that the sealant 111 is a polymer material, it is accessible to have reactions with the liquid crystal, even overflow to a sensor area, which has a die 103. In order to have a safe distance between the sealant 111 and the sensor area, the dimension of the device is not simple to shrink so that the gross dies of a wafer will be decreased, more, the yield is also not improved.
By the processes of the traditional packaging or TFT-LCD process as mentioned above, the position and width of the sealant are not to be precisely and effectively controlled. Therefore, an improved method of packaging is required in order to overcome the problems of the packaging in the prior art.